1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and the semiconductor device, and especially relates to a manufacturing method of a semiconductor device and the semiconductor device with which a loop back test is performed.
2. Description of the Background Art
By advanced features and speeding up of digital information apparatus, network equipment, etc., an implementation of a high-speed interface (a data transfer rate being 1 Gbps or more) is progressing with the semiconductor for communication. In order to carry out the mass production test of the semiconductor device carrying a high-speed interface as usual at a real operation speed, i.e., speed used as a product, the expensive highly efficient circuit tester for examining a semiconductor device is needed, and it leads to the jump of test cost. However, the unit price of the product with which a semiconductor device is incorporated tends to fall, and reduction of test cost is demanded.
Then, the loop back test technique attracts attention as the technique of carrying out the AC (alternating current) characteristics test (it also being hereafter called an AC test.) of a high-speed interface, without using a highly efficient circuit tester. The loop back test technique is the technique of turning and inputting the signal outputted from the driver with which a semiconductor device is provided into the receiver with which a semiconductor device is provided, and judging the function of a semiconductor device at real operation speed.
As an equipment which tests a semiconductor device, the following semiconductor test equipment is disclosed by Japanese Patent Laying-Open No. 2003-255022 (Patent Reference 1), for example. That is, a changeover switch is formed and it has structure which can choose the input signal from the other devices connected in real operation, or the input signal from measuring apparatus for the input signal to a device under test. Then, it measures by connecting with measuring apparatus at measurement of a DC low-speed signal level. At measurement of the high speed signal which cannot deal with in the input signal from measuring apparatus, it connects with other devices, high-speed operation of the device under test is performed, and only the output signal is measured with measuring apparatus.
The following semiconductor test equipment is disclosed by Japanese Patent Laying-Open No. 11-160388 (Patent Reference 2). That is, it is provided with a plurality of power supply circuits which supply a power supply individually for every power supply terminal of a plurality of devices under test, the capacitor for low frequency connected in parallel with each power supply circuit, the relay by which it was formed for this every capacitor and the point of contact was connected to this capacitor at series, respectively, and the power supply circuit for loads for the load circuit on a test board. The exiting coil of a relay is driven with the voltage of the power supply circuit for loads. The semiconductor test equipment which does a loop back test is disclosed by Japanese Patent Laying-Open No. 2000-171524 (Patent Reference 3) and Japanese Patent Laying-Open No. 2003-167034 (Patent Reference 4).
However, the semiconductor test equipment described in Patent Reference 1 and Patent Reference 2 is not provided with the structure which does a loop back test. When it connects simply the driver and receiver which are the interface circuitries of the semiconductor device which is a test objective like semiconductor test equipment described in Patent Reference 3 and Patent Reference 4, in order to do a loop back test, the DC (direct current) characteristic test (it is also hereafter called a DC test.), for example measuring the potential in an output of the driver and the potential in an input of the driver, respectively of a semiconductor device cannot be performed. That is, a receiver does not have the function to judge the DC characteristic of a driver (transmitter), and a driver does not have the function to judge a receiver's DC characteristic either. Therefore, where a driver and a receiver are short-circuited, the DC characteristic of a driver and a receiver cannot be judged, respectively. Therefore, when the wiring for loop back tests was formed on a test board and a loop back test was performed at the test (it is also hereafter called final test FT.) step performed in the state where dicing etc. was performed to the semiconductor chip on a silicon wafer, and it was package-ized, a DC test was not able to be performed in the final test process. Therefore, it is necessary to do a DC test at a test process other than a final test process, concretely in the test (it is also hereafter called wafer test WT.) step performed in the state where the semiconductor chip is mounted on the silicon wafer, and to do a loop back test in a final test process.
Here, in a DC test, a probe is applied to the bonding pad, i.e., the electrode, of a semiconductor device of a wafer state, and supply, measurement, etc. of voltage are performed. However, when a probe is applied to a bonding pad, a bonding pad will get damaged, and adhesion of a bonding wire will be difficult. So, in order to fully secure the region to which a probe is applied, and the region which pastes up a bonding wire, it is necessary to enlarge area of a bonding pad. When it does so, the parasitic capacitance to a bonding pad will become large, and the AC characteristics of a semiconductor device will deteriorate. For this reason, especially about the bonding pad for a high-speed interface, it becomes difficult to enlarge area of a bonding pad and to fully secure the region to which a probe is applied, and the region which pastes up a bonding wire. It will become impossible to do the DC test of a high-speed interface circuitry to the semiconductor device of a wafer state.